1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a random access memory (RAM) having a bipolar static memory cells with PNPN transistors wherein the operating speed is improved by controlling the current amplification factor of the NPN transistors in each memory cell.
2. Description of the Prior Art
A typical semiconductor memory is comprised of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells located at the intersections of the word lines and bit lines. Semiconductor memories utilize various types of memory cells. The present invention relates to a semiconductor memory utilizing saturation-type memory cells.
Generally, in such a semiconductor memory, that is, a static semiconductor memory, a so-called holding current flows through each memory cell so as to maintain the stored data of logic "1" or "0". When the memory cell is changed from a half selected state to a nonselected state, electric charges stored in the parasitic capacitances of the cell are discharged by the holding current. The greater the holding current, the faster the switching speed from the half selected state to the nonselected state. However, from the view point of large memory capacity and low power consumption, the discharged holding current (I.sub.H) should preferably be small. Thus, it is difficult to increase the switching speed by making the holding current large. One previous proposal to get around this problem and achieve a fast switching speed is to have a discharging current (I.sub.DS) selectively absorbed from a selected word line.
In a semiconductor memory, the emitter voltage of a detection transistor, i.e., a read/write transistor, in each half selected memory cell is usually raised to a high level to prevent adverse influences of a sink current as hereinafter described in detail. However, when the emitter voltage is raised to a high level, the detection transistor operates inversely, as herein described in detail, so that a part of the discharging current (I.sub.DS) from the word line is unnecessarily branched as a sink current into the bit line connected to the detection transistor of each half selected memory cell. This sink current adversely affects the rising speed of the word line potential. Conventionally, in order to prevent the deterioration of the rising speed of the word line, a bit-line clamping circuit for clamping nonselected bit lines to a level higher than the level of the selected word line is provided. However, in this case, the sink current also flows through each half selected memory cell in the selected word line. The sink current i.sub.SNK for each memory cell is expressed as: i.sub.SNK =.gamma.(i.sub.H +i.sub.DS), where .gamma. is a factor proportional to the current amplification factor .beta.u of the detection transistor when it is operated inversely, and i.sub.H and i.sub.DS are a holding current and a discharging current for each memory cell, respectively. It is preferable that the sink current i.sub.SNK be as small as possible so as to ensure a fast switching operation.